// Copyright (C) 2022 Beken Corporation
// 
// Licensed under the Apache License, Version 2.0 (the "License");           
// you may not use this file except in compliance with the License.            
// You may obtain a copy of the License at                                     
//                                                                             
//     http://www.apache.org/licenses/LICENSE-2.0                              
//                                                                             
// Unless required by applicable law or agreed to in writing, software         
// distributed under the License is distributed on an "AS IS" BASIS,         
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.    
// See the License for the specific language governing permissions and         
// limitations under the License.                                              

#pragma once                 
                            
#ifdef __cplusplus          
extern "C" {              
#endif                      

#define AUD_LL_REG_BASE      (SOC_AUD_REG_BASE)

/* REG_0x00 */
#define AUD_AUDIO_CONFIG_ADDR  (AUD_LL_REG_BASE  + 0x0*4)
#define AUD_AUDIO_CONFIG_SAMP_RATE_ADC_POS (0) 
#define AUD_AUDIO_CONFIG_SAMP_RATE_ADC_MASK (0x3) 

#define AUD_AUDIO_CONFIG_DAC_ENABLE_POS (2) 
#define AUD_AUDIO_CONFIG_DAC_ENABLE_MASK (0x1) 

#define AUD_AUDIO_CONFIG_ADC_ENABLE_POS (3) 
#define AUD_AUDIO_CONFIG_ADC_ENABLE_MASK (0x1) 

#define AUD_AUDIO_CONFIG_DTMF_ENABLE_POS (4) 
#define AUD_AUDIO_CONFIG_DTMF_ENABLE_MASK (0x1) 

#define AUD_AUDIO_CONFIG_LINE_ENABLE_POS (5) 
#define AUD_AUDIO_CONFIG_LINE_ENABLE_MASK (0x1) 

#define AUD_AUDIO_CONFIG_SAMP_RATE_DAC_POS (6) 
#define AUD_AUDIO_CONFIG_SAMP_RATE_DAC_MASK (0x3) 

#define AUD_AUDIO_CONFIG_RESERVED_POS (8) 
#define AUD_AUDIO_CONFIG_RESERVED_MASK (0xFFFFFF) 

/* REG_0x01 */
#define AUD_DTMF_CONFIG0_ADDR  (AUD_LL_REG_BASE  + 0x1*4)
#define AUD_DTMF_CONFIG0_TONE_PATTERN_POS (0) 
#define AUD_DTMF_CONFIG0_TONE_PATTERN_MASK (0x1) 

#define AUD_DTMF_CONFIG0_TONE_MODE_POS (1) 
#define AUD_DTMF_CONFIG0_TONE_MODE_MASK (0x1) 

#define AUD_DTMF_CONFIG0_TONE_PAUSE_TIME_POS (2) 
#define AUD_DTMF_CONFIG0_TONE_PAUSE_TIME_MASK (0xF) 

#define AUD_DTMF_CONFIG0_TONE_ACTIVE_TIME_POS (6) 
#define AUD_DTMF_CONFIG0_TONE_ACTIVE_TIME_MASK (0xF) 

#define AUD_DTMF_CONFIG0_RESERVED_POS (10) 
#define AUD_DTMF_CONFIG0_RESERVED_MASK (0x3FFFFF) 

/* REG_0x02 */
#define AUD_DTMF_CONFIG1_ADDR  (AUD_LL_REG_BASE  + 0x2*4)
#define AUD_DTMF_CONFIG1_TONE1_STEP_POS (0) 
#define AUD_DTMF_CONFIG1_TONE1_STEP_MASK (0xFFFF) 

#define AUD_DTMF_CONFIG1_TONE1_ATTU_POS (16) 
#define AUD_DTMF_CONFIG1_TONE1_ATTU_MASK (0xF) 

#define AUD_DTMF_CONFIG1_TONE1_ENABLE_POS (20) 
#define AUD_DTMF_CONFIG1_TONE1_ENABLE_MASK (0x1) 

#define AUD_DTMF_CONFIG1_RESERVED_POS (21) 
#define AUD_DTMF_CONFIG1_RESERVED_MASK (0x7FF) 

/* REG_0x03 */
#define AUD_DTMF_CONFIG2_ADDR  (AUD_LL_REG_BASE  + 0x3*4)
#define AUD_DTMF_CONFIG2_TONE2_STEP_POS (0) 
#define AUD_DTMF_CONFIG2_TONE2_STEP_MASK (0xFFFF) 

#define AUD_DTMF_CONFIG2_TONE2_ATTU_POS (16) 
#define AUD_DTMF_CONFIG2_TONE2_ATTU_MASK (0xF) 

#define AUD_DTMF_CONFIG2_TONE2_ENABLE_POS (20) 
#define AUD_DTMF_CONFIG2_TONE2_ENABLE_MASK (0x1) 

#define AUD_DTMF_CONFIG2_RESERVED_POS (21) 
#define AUD_DTMF_CONFIG2_RESERVED_MASK (0x7FF) 

/* REG_0x04 */
#define AUD_ADC_CONFIG0_ADDR  (AUD_LL_REG_BASE  + 0x4*4)
#define AUD_ADC_CONFIG0_ADC_HPF2_COEF_B2_POS (0) 
#define AUD_ADC_CONFIG0_ADC_HPF2_COEF_B2_MASK (0xFFFF) 

#define AUD_ADC_CONFIG0_ADC_HPF2_BYPASS_POS (16) 
#define AUD_ADC_CONFIG0_ADC_HPF2_BYPASS_MASK (0x1) 

#define AUD_ADC_CONFIG0_ADC_HPF1_BYPASS_POS (17) 
#define AUD_ADC_CONFIG0_ADC_HPF1_BYPASS_MASK (0x1) 

#define AUD_ADC_CONFIG0_ADC_SET_GAIN_POS (18) 
#define AUD_ADC_CONFIG0_ADC_SET_GAIN_MASK (0x3F) 

#define AUD_ADC_CONFIG0_ADC_SAMPE_EDGE_POS (24) 
#define AUD_ADC_CONFIG0_ADC_SAMPE_EDGE_MASK (0x1) 

#define AUD_ADC_CONFIG0_RESERVED_POS (25) 
#define AUD_ADC_CONFIG0_RESERVED_MASK (0x7F) 

/* REG_0x05 */
#define AUD_ADC_CONFIG1_ADDR  (AUD_LL_REG_BASE  + 0x5*4)
#define AUD_ADC_CONFIG1_ADC_HPF2_COEF_B0_POS (0) 
#define AUD_ADC_CONFIG1_ADC_HPF2_COEF_B0_MASK (0xFFFF) 

#define AUD_ADC_CONFIG1_ADC_HPF2_COEF_B1_POS (16) 
#define AUD_ADC_CONFIG1_ADC_HPF2_COEF_B1_MASK (0xFFFF) 

/* REG_0x06 */
#define AUD_ADC_CONFIG2_ADDR  (AUD_LL_REG_BASE  + 0x6*4)
#define AUD_ADC_CONFIG2_ADC_HPF2_COEF_A0_POS (0) 
#define AUD_ADC_CONFIG2_ADC_HPF2_COEF_A0_MASK (0xFFFF) 

#define AUD_ADC_CONFIG2_ADC_HPF2_COEF_A1_POS (16) 
#define AUD_ADC_CONFIG2_ADC_HPF2_COEF_A1_MASK (0xFFFF) 

/* REG_0x07 */
#define AUD_DAC_CONFIG0_ADDR  (AUD_LL_REG_BASE  + 0x7*4)
#define AUD_DAC_CONFIG0_DAC_HPF2_COEF_B2_POS (0) 
#define AUD_DAC_CONFIG0_DAC_HPF2_COEF_B2_MASK (0xFFFF) 

#define AUD_DAC_CONFIG0_DAC_HPF2_BYPASS_POS (16) 
#define AUD_DAC_CONFIG0_DAC_HPF2_BYPASS_MASK (0x1) 

#define AUD_DAC_CONFIG0_DAC_HPF1_BYPASS_POS (17) 
#define AUD_DAC_CONFIG0_DAC_HPF1_BYPASS_MASK (0x1) 

#define AUD_DAC_CONFIG0_DAC_SET_GAIN_POS (18) 
#define AUD_DAC_CONFIG0_DAC_SET_GAIN_MASK (0x3F) 

#define AUD_DAC_CONFIG0_DAC_CLK_INVERT_POS (24) 
#define AUD_DAC_CONFIG0_DAC_CLK_INVERT_MASK (0x1) 

#define AUD_DAC_CONFIG0_RESERVED_POS (25) 
#define AUD_DAC_CONFIG0_RESERVED_MASK (0x7F) 

/* REG_0x08 */
#define AUD_DAC_CONFIG1_ADDR  (AUD_LL_REG_BASE  + 0x8*4)
#define AUD_DAC_CONFIG1_DAC_HPF2_COEF_B0_POS (0) 
#define AUD_DAC_CONFIG1_DAC_HPF2_COEF_B0_MASK (0xFFFF) 

#define AUD_DAC_CONFIG1_DAC_HPF2_COEF_B1_POS (16) 
#define AUD_DAC_CONFIG1_DAC_HPF2_COEF_B1_MASK (0xFFFF) 

/* REG_0x09 */
#define AUD_DAC_CONFIG2_ADDR  (AUD_LL_REG_BASE  + 0x9*4)
#define AUD_DAC_CONFIG2_DAC_HPF2_COEF_A1_POS (0) 
#define AUD_DAC_CONFIG2_DAC_HPF2_COEF_A1_MASK (0xFFFF) 

#define AUD_DAC_CONFIG2_DAC_HPF2_COEF_A2_POS (16) 
#define AUD_DAC_CONFIG2_DAC_HPF2_COEF_A2_MASK (0xFFFF) 

/* REG_0x0A */
#define AUD_FIFO_CONFIG_ADDR  (AUD_LL_REG_BASE  + 0xA*4)
#define AUD_FIFO_CONFIG_DACR_RD_THRESHOLD_POS (0) 
#define AUD_FIFO_CONFIG_DACR_RD_THRESHOLD_MASK (0x1F) 

#define AUD_FIFO_CONFIG_DACL_RD_THRESHOLD_POS (5) 
#define AUD_FIFO_CONFIG_DACL_RD_THRESHOLD_MASK (0x1F) 

#define AUD_FIFO_CONFIG_DTMF_WR_THRESHOLD_POS (10) 
#define AUD_FIFO_CONFIG_DTMF_WR_THRESHOLD_MASK (0x1F) 

#define AUD_FIFO_CONFIG_ADCL_WR_THRESHOLD_POS (15) 
#define AUD_FIFO_CONFIG_ADCL_WR_THRESHOLD_MASK (0x1F) 

#define AUD_FIFO_CONFIG_DACR_INT_EN_POS (20) 
#define AUD_FIFO_CONFIG_DACR_INT_EN_MASK (0x1) 

#define AUD_FIFO_CONFIG_DACL_INT_EN_POS (21) 
#define AUD_FIFO_CONFIG_DACL_INT_EN_MASK (0x1) 

#define AUD_FIFO_CONFIG_DTMF_INT_EN_POS (22) 
#define AUD_FIFO_CONFIG_DTMF_INT_EN_MASK (0x1) 

#define AUD_FIFO_CONFIG_ADCL_INT_EN_POS (23) 
#define AUD_FIFO_CONFIG_ADCL_INT_EN_MASK (0x1) 

#define AUD_FIFO_CONFIG_LOOP_TON2DAC_POS (24) 
#define AUD_FIFO_CONFIG_LOOP_TON2DAC_MASK (0x1) 

#define AUD_FIFO_CONFIG_LOOP_ADC2DAC_POS (25) 
#define AUD_FIFO_CONFIG_LOOP_ADC2DAC_MASK (0x1) 

#define AUD_FIFO_CONFIG_RESERVED_POS (26) 
#define AUD_FIFO_CONFIG_RESERVED_MASK (0x3F) 

/* REG_0x0B */
#define AUD_AGC_CONFIG0_ADDR  (AUD_LL_REG_BASE  + 0xB*4)
#define AUD_AGC_CONFIG0_AGC_NOISE_THRD_POS (0) 
#define AUD_AGC_CONFIG0_AGC_NOISE_THRD_MASK (0x3FF) 

#define AUD_AGC_CONFIG0_AGC_NOISE_HIGH_POS (10) 
#define AUD_AGC_CONFIG0_AGC_NOISE_HIGH_MASK (0x3FF) 

#define AUD_AGC_CONFIG0_AGC_NOISE_LOW_POS (20) 
#define AUD_AGC_CONFIG0_AGC_NOISE_LOW_MASK (0x3FF) 

#define AUD_AGC_CONFIG0_AGC_STEP_POS (30) 
#define AUD_AGC_CONFIG0_AGC_STEP_MASK (0x3) 

/* REG_0x0C */
#define AUD_AGC_CONFIG1_ADDR  (AUD_LL_REG_BASE  + 0xC*4)
#define AUD_AGC_CONFIG1_AGC_NOISE_MIN_POS (0) 
#define AUD_AGC_CONFIG1_AGC_NOISE_MIN_MASK (0x7F) 

#define AUD_AGC_CONFIG1_AGC_NOISE_TOUT_POS (7) 
#define AUD_AGC_CONFIG1_AGC_NOISE_TOUT_MASK (0x7) 

#define AUD_AGC_CONFIG1_AGC_HIGH_DUR_POS (10) 
#define AUD_AGC_CONFIG1_AGC_HIGH_DUR_MASK (0x7) 

#define AUD_AGC_CONFIG1_AGC_LOW_DUR_POS (13) 
#define AUD_AGC_CONFIG1_AGC_LOW_DUR_MASK (0x7) 

#define AUD_AGC_CONFIG1_AGC_MIN_POS (16) 
#define AUD_AGC_CONFIG1_AGC_MIN_MASK (0x7F) 

#define AUD_AGC_CONFIG1_AGC_MAX_POS (23) 
#define AUD_AGC_CONFIG1_AGC_MAX_MASK (0x7F) 

#define AUD_AGC_CONFIG1_AGC_NG_METHOD_POS (30) 
#define AUD_AGC_CONFIG1_AGC_NG_METHOD_MASK (0x1) 

#define AUD_AGC_CONFIG1_AGC_NG_ENABLE_POS (31) 
#define AUD_AGC_CONFIG1_AGC_NG_ENABLE_MASK (0x1) 

/* REG_0x0D */
#define AUD_AGC_CONFIG2_ADDR  (AUD_LL_REG_BASE  + 0xD*4)
#define AUD_AGC_CONFIG2_AGC_DECAY_TIME_POS (0) 
#define AUD_AGC_CONFIG2_AGC_DECAY_TIME_MASK (0x7) 

#define AUD_AGC_CONFIG2_AGC_ATTACK_TIME_POS (3) 
#define AUD_AGC_CONFIG2_AGC_ATTACK_TIME_MASK (0x7) 

#define AUD_AGC_CONFIG2_AGC_HIGH_THRD_POS (6) 
#define AUD_AGC_CONFIG2_AGC_HIGH_THRD_MASK (0x1F) 

#define AUD_AGC_CONFIG2_AGC_LOW_THRD_POS (11) 
#define AUD_AGC_CONFIG2_AGC_LOW_THRD_MASK (0x1F) 

#define AUD_AGC_CONFIG2_AGC_IIR_COEF_POS (16) 
#define AUD_AGC_CONFIG2_AGC_IIR_COEF_MASK (0x7) 

#define AUD_AGC_CONFIG2_AGC_ENABLE_POS (19) 
#define AUD_AGC_CONFIG2_AGC_ENABLE_MASK (0x1) 

#define AUD_AGC_CONFIG2_MANUAL_PGA_VALUE_POS (20) 
#define AUD_AGC_CONFIG2_MANUAL_PGA_VALUE_MASK (0x7F) 

#define AUD_AGC_CONFIG2_MANUAL_PGA_POS (27) 
#define AUD_AGC_CONFIG2_MANUAL_PGA_MASK (0x1) 

#define AUD_AGC_CONFIG2_RESERVED_POS (28) 
#define AUD_AGC_CONFIG2_RESERVED_MASK (0xF) 

/* REG_0x0E */
#define AUD_FIFO_STATUS_ADDR  (AUD_LL_REG_BASE  + 0xE*4)
#define AUD_FIFO_STATUS_DACR_NEAR_FULL_POS (0) 
#define AUD_FIFO_STATUS_DACR_NEAR_FULL_MASK (0x1) 

#define AUD_FIFO_STATUS_DACL_NEAR_FULL_POS (1) 
#define AUD_FIFO_STATUS_DACL_NEAR_FULL_MASK (0x1) 

#define AUD_FIFO_STATUS_ADCL_NEAR_FULL_POS (2) 
#define AUD_FIFO_STATUS_ADCL_NEAR_FULL_MASK (0x1) 

#define AUD_FIFO_STATUS_DTMF_NEAR_FULL_POS (3) 
#define AUD_FIFO_STATUS_DTMF_NEAR_FULL_MASK (0x1) 

#define AUD_FIFO_STATUS_DACR_NEAR_EMPTY_POS (4) 
#define AUD_FIFO_STATUS_DACR_NEAR_EMPTY_MASK (0x1) 

#define AUD_FIFO_STATUS_DACL_NEAR_EMPTY_POS (5) 
#define AUD_FIFO_STATUS_DACL_NEAR_EMPTY_MASK (0x1) 

#define AUD_FIFO_STATUS_ADCL_NEAR_EMPTY_POS (6) 
#define AUD_FIFO_STATUS_ADCL_NEAR_EMPTY_MASK (0x1) 

#define AUD_FIFO_STATUS_DTMF_NEAR_EMPTY_POS (7) 
#define AUD_FIFO_STATUS_DTMF_NEAR_EMPTY_MASK (0x1) 

#define AUD_FIFO_STATUS_DACR_FIFO_FULL_POS (8) 
#define AUD_FIFO_STATUS_DACR_FIFO_FULL_MASK (0x1) 

#define AUD_FIFO_STATUS_DACL_FIFO_FULL_POS (9) 
#define AUD_FIFO_STATUS_DACL_FIFO_FULL_MASK (0x1) 

#define AUD_FIFO_STATUS_ADCL_FIFO_FULL_POS (10) 
#define AUD_FIFO_STATUS_ADCL_FIFO_FULL_MASK (0x1) 

#define AUD_FIFO_STATUS_DTMF_FIFO_FULL_POS (11) 
#define AUD_FIFO_STATUS_DTMF_FIFO_FULL_MASK (0x1) 

#define AUD_FIFO_STATUS_DACR_FIFO_EMPTY_POS (12) 
#define AUD_FIFO_STATUS_DACR_FIFO_EMPTY_MASK (0x1) 

#define AUD_FIFO_STATUS_DACL_FIFO_EMPTY_POS (13) 
#define AUD_FIFO_STATUS_DACL_FIFO_EMPTY_MASK (0x1) 

#define AUD_FIFO_STATUS_ADCL_FIFO_EMPTY_POS (14) 
#define AUD_FIFO_STATUS_ADCL_FIFO_EMPTY_MASK (0x1) 

#define AUD_FIFO_STATUS_DTMF_FIFO_EMPTY_POS (15) 
#define AUD_FIFO_STATUS_DTMF_FIFO_EMPTY_MASK (0x1) 

#define AUD_FIFO_STATUS_DACR_INT_FLAG_POS (16) 
#define AUD_FIFO_STATUS_DACR_INT_FLAG_MASK (0x1) 

#define AUD_FIFO_STATUS_DACL_INT_FLAG_POS (17) 
#define AUD_FIFO_STATUS_DACL_INT_FLAG_MASK (0x1) 

#define AUD_FIFO_STATUS_ADCL_INT_FLAG_POS (18) 
#define AUD_FIFO_STATUS_ADCL_INT_FLAG_MASK (0x1) 

#define AUD_FIFO_STATUS_DTMF_INT_FLAG_POS (19) 
#define AUD_FIFO_STATUS_DTMF_INT_FLAG_MASK (0x1) 

#define AUD_FIFO_STATUS_RESERVED_POS (20) 
#define AUD_FIFO_STATUS_RESERVED_MASK (0xFFF) 

/* REG_0x0F */
#define AUD_AGC_STATUS_ADDR  (AUD_LL_REG_BASE  + 0xF*4)
#define AUD_AGC_STATUS_RSSI_POS (0) 
#define AUD_AGC_STATUS_RSSI_MASK (0xFF) 

#define AUD_AGC_STATUS_MIC_PGA_POS (8) 
#define AUD_AGC_STATUS_MIC_PGA_MASK (0xFF) 

#define AUD_AGC_STATUS_MIC_RSSI_POS (16) 
#define AUD_AGC_STATUS_MIC_RSSI_MASK (0xFFFF) 

/* REG_0x10 */
#define AUD_DTMF_FPORT_ADDR  (AUD_LL_REG_BASE  + 0x10*4)
#define AUD_DTMF_FPORT_DTMF_PORT_POS (0) 
#define AUD_DTMF_FPORT_DTMF_PORT_MASK (0xFFFF) 

#define AUD_DTMF_FPORT_RESERVED_POS (16) 
#define AUD_DTMF_FPORT_RESERVED_MASK (0xFFFF) 

/* REG_0x11 */
#define AUD_ADC_FPORT_ADDR  (AUD_LL_REG_BASE  + 0x11*4)
#define AUD_ADC_FPORT_ADC_PORT_POS (0) 
#define AUD_ADC_FPORT_ADC_PORT_MASK (0xFFFF) 

#define AUD_ADC_FPORT_RESERVED_POS (16) 
#define AUD_ADC_FPORT_RESERVED_MASK (0xFFFF) 

/* REG_0x12 */
#define AUD_DACL_FPORT_ADDR  (AUD_LL_REG_BASE  + 0x12*4)
#define AUD_DACL_FPORT_DACL_PORT_POS (0) 
#define AUD_DACL_FPORT_DACL_PORT_MASK (0xFFFF) 

#define AUD_DACL_FPORT_DACR_PORT_POS (16) 
#define AUD_DACL_FPORT_DACR_PORT_MASK (0xFFFF) 

/* REG_0x18 */
#define AUD_EXTEND_CFG_ADDR  (AUD_LL_REG_BASE  + 0x18*4)
#define AUD_EXTEND_CFG_DAC_FRACMOD_MANUAL_POS (0) 
#define AUD_EXTEND_CFG_DAC_FRACMOD_MANUAL_MASK (0x1) 

#define AUD_EXTEND_CFG_ADC_FRACMOD_MANUAL_POS (1) 
#define AUD_EXTEND_CFG_ADC_FRACMOD_MANUAL_MASK (0x1) 

#define AUD_EXTEND_CFG_FILT_ENABLE_POS (2) 
#define AUD_EXTEND_CFG_FILT_ENABLE_MASK (0x1) 

#define AUD_EXTEND_CFG_RESERVED_POS (3) 
#define AUD_EXTEND_CFG_RESERVED_MASK (0x1FFFFFFF) 

/* REG_0x19 */
#define AUD_DAC_FRACMOD_ADDR  (AUD_LL_REG_BASE  + 0x19*4)
#define AUD_DAC_FRACMOD_DAC_FRACCOEF_POS (0) 
#define AUD_DAC_FRACMOD_DAC_FRACCOEF_MASK (0xFFFFFFFF) 

/* REG_0x1A */
#define AUD_ADC_FRACMOD_ADDR  (AUD_LL_REG_BASE  + 0x1A*4)
#define AUD_ADC_FRACMOD_ADC_FRACCOEF_POS (0) 
#define AUD_ADC_FRACMOD_ADC_FRACCOEF_MASK (0xFFFFFFFF) 

/* REG_0x1F */
#define AUD_HPF2_EXT_COEF_ADDR  (AUD_LL_REG_BASE  + 0x1F*4)
#define AUD_HPF2_EXT_COEF_HPF2_A1_L6BIT_POS (0) 
#define AUD_HPF2_EXT_COEF_HPF2_A1_L6BIT_MASK (0x3F) 

#define AUD_HPF2_EXT_COEF_HPF2_A2_L6BIT_POS (6) 
#define AUD_HPF2_EXT_COEF_HPF2_A2_L6BIT_MASK (0x3F) 

#define AUD_HPF2_EXT_COEF_HPF2_B0_L6BIT_POS (12) 
#define AUD_HPF2_EXT_COEF_HPF2_B0_L6BIT_MASK (0x3F) 

#define AUD_HPF2_EXT_COEF_HPF2_B1_L6BIT_POS (18) 
#define AUD_HPF2_EXT_COEF_HPF2_B1_L6BIT_MASK (0x3F) 

#define AUD_HPF2_EXT_COEF_HPF2_B2_L6BIT_POS (24) 
#define AUD_HPF2_EXT_COEF_HPF2_B2_L6BIT_MASK (0x3F) 

#define AUD_HPF2_EXT_COEF_RESERVED_POS (30) 
#define AUD_HPF2_EXT_COEF_RESERVED_MASK (0x3) 

/* REG_0x20 */
#define AUD_FLT0_COEF_A1A2_ADDR  (AUD_LL_REG_BASE  + 0x20*4)
#define AUD_FLT0_COEF_A1A2_FLT0_A1_POS (0) 
#define AUD_FLT0_COEF_A1A2_FLT0_A1_MASK (0xFFFF) 

#define AUD_FLT0_COEF_A1A2_FLT0_A2_POS (16) 
#define AUD_FLT0_COEF_A1A2_FLT0_A2_MASK (0xFFFF) 

/* REG_0x21 */
#define AUD_FLT0_COEF_B0B1_ADDR  (AUD_LL_REG_BASE  + 0x21*4)
#define AUD_FLT0_COEF_B0B1_FLT0_B0_POS (0) 
#define AUD_FLT0_COEF_B0B1_FLT0_B0_MASK (0xFFFF) 

#define AUD_FLT0_COEF_B0B1_FLT0_B1_POS (16) 
#define AUD_FLT0_COEF_B0B1_FLT0_B1_MASK (0xFFFF) 

/* REG_0x22 */
#define AUD_FLT0_COEF_B2_ADDR  (AUD_LL_REG_BASE  + 0x22*4)
#define AUD_FLT0_COEF_B2_FLT0_B2_POS (0) 
#define AUD_FLT0_COEF_B2_FLT0_B2_MASK (0xFFFF) 

#define AUD_FLT0_COEF_B2_RESERVED_POS (16) 
#define AUD_FLT0_COEF_B2_RESERVED_MASK (0xFFFF) 

/* REG_0x23 */
#define AUD_FLT1_COEF_A1A2_ADDR  (AUD_LL_REG_BASE  + 0x23*4)
#define AUD_FLT1_COEF_A1A2_FLT1_A1_POS (0) 
#define AUD_FLT1_COEF_A1A2_FLT1_A1_MASK (0xFFFF) 

#define AUD_FLT1_COEF_A1A2_FLT1_A2_POS (16) 
#define AUD_FLT1_COEF_A1A2_FLT1_A2_MASK (0xFFFF) 

/* REG_0x24 */
#define AUD_FLT1_COEF_B0B1_ADDR  (AUD_LL_REG_BASE  + 0x24*4)
#define AUD_FLT1_COEF_B0B1_FLT1_B0_POS (0) 
#define AUD_FLT1_COEF_B0B1_FLT1_B0_MASK (0xFFFF) 

#define AUD_FLT1_COEF_B0B1_FLT1_B1_POS (16) 
#define AUD_FLT1_COEF_B0B1_FLT1_B1_MASK (0xFFFF) 

/* REG_0x25 */
#define AUD_FLT1_COEF_B2_ADDR  (AUD_LL_REG_BASE  + 0x25*4)
#define AUD_FLT1_COEF_B2_FLT1_B2_POS (0) 
#define AUD_FLT1_COEF_B2_FLT1_B2_MASK (0xFFFF) 

#define AUD_FLT1_COEF_B2_RESERVED_POS (16) 
#define AUD_FLT1_COEF_B2_RESERVED_MASK (0xFFFF) 

/* REG_0x26 */
#define AUD_FLT2_COEF_A1A2_ADDR  (AUD_LL_REG_BASE  + 0x26*4)
#define AUD_FLT2_COEF_A1A2_FLT2_A1_POS (0) 
#define AUD_FLT2_COEF_A1A2_FLT2_A1_MASK (0xFFFF) 

#define AUD_FLT2_COEF_A1A2_FLT2_A2_POS (16) 
#define AUD_FLT2_COEF_A1A2_FLT2_A2_MASK (0xFFFF) 

/* REG_0x27 */
#define AUD_FLT2_COEF_B0B1_ADDR  (AUD_LL_REG_BASE  + 0x27*4)
#define AUD_FLT2_COEF_B0B1_FLT2_B0_POS (0) 
#define AUD_FLT2_COEF_B0B1_FLT2_B0_MASK (0xFFFF) 

#define AUD_FLT2_COEF_B0B1_FLT2_B1_POS (16) 
#define AUD_FLT2_COEF_B0B1_FLT2_B1_MASK (0xFFFF) 

/* REG_0x28 */
#define AUD_FLT2_COEF_B2_ADDR  (AUD_LL_REG_BASE  + 0x28*4)
#define AUD_FLT2_COEF_B2_FLT2_B2_POS (0) 
#define AUD_FLT2_COEF_B2_FLT2_B2_MASK (0xFFFF) 

#define AUD_FLT2_COEF_B2_RESERVED_POS (16) 
#define AUD_FLT2_COEF_B2_RESERVED_MASK (0xFFFF) 

/* REG_0x29 */
#define AUD_FLT3_COEF_A1A2_ADDR  (AUD_LL_REG_BASE  + 0x29*4)
#define AUD_FLT3_COEF_A1A2_FLT3_A1_POS (0) 
#define AUD_FLT3_COEF_A1A2_FLT3_A1_MASK (0xFFFF) 

#define AUD_FLT3_COEF_A1A2_FLT3_A2_POS (16) 
#define AUD_FLT3_COEF_A1A2_FLT3_A2_MASK (0xFFFF) 

/* REG_0x2A */
#define AUD_FLT3_COEF_B0B1_ADDR  (AUD_LL_REG_BASE  + 0x2A*4)
#define AUD_FLT3_COEF_B0B1_FLT3_B0_POS (0) 
#define AUD_FLT3_COEF_B0B1_FLT3_B0_MASK (0xFFFF) 

#define AUD_FLT3_COEF_B0B1_FLT3_B1_POS (16) 
#define AUD_FLT3_COEF_B0B1_FLT3_B1_MASK (0xFFFF) 

/* REG_0x2B */
#define AUD_FLT3_COEF_B2_ADDR  (AUD_LL_REG_BASE  + 0x2B*4)
#define AUD_FLT3_COEF_B2_FLT3_B2_POS (0) 
#define AUD_FLT3_COEF_B2_FLT3_B2_MASK (0xFFFF) 

#define AUD_FLT3_COEF_B2_RESERVED_POS (16) 
#define AUD_FLT3_COEF_B2_RESERVED_MASK (0xFFFF) 

/* REG_0x2C */
#define AUD_FLT0_EXT_COEF_ADDR  (AUD_LL_REG_BASE  + 0x2C*4)
#define AUD_FLT0_EXT_COEF_FLT0_A1_L6BIT_POS (0) 
#define AUD_FLT0_EXT_COEF_FLT0_A1_L6BIT_MASK (0x3F) 

#define AUD_FLT0_EXT_COEF_FLT0_A2_L6BIT_POS (6) 
#define AUD_FLT0_EXT_COEF_FLT0_A2_L6BIT_MASK (0x3F) 

#define AUD_FLT0_EXT_COEF_FLT0_B0_L6BIT_POS (12) 
#define AUD_FLT0_EXT_COEF_FLT0_B0_L6BIT_MASK (0x3F) 

#define AUD_FLT0_EXT_COEF_FLT0_B1_L6BIT_POS (18) 
#define AUD_FLT0_EXT_COEF_FLT0_B1_L6BIT_MASK (0x3F) 

#define AUD_FLT0_EXT_COEF_FLT0_B2_L6BIT_POS (24) 
#define AUD_FLT0_EXT_COEF_FLT0_B2_L6BIT_MASK (0x3F) 

#define AUD_FLT0_EXT_COEF_RESERVED_POS (30) 
#define AUD_FLT0_EXT_COEF_RESERVED_MASK (0x3) 

/* REG_0x2D */
#define AUD_FLT1_EXT_COEF_ADDR  (AUD_LL_REG_BASE  + 0x2D*4)
#define AUD_FLT1_EXT_COEF_FLT1_A1_L6BIT_POS (0) 
#define AUD_FLT1_EXT_COEF_FLT1_A1_L6BIT_MASK (0x3F) 

#define AUD_FLT1_EXT_COEF_FLT1_A2_L6BIT_POS (6) 
#define AUD_FLT1_EXT_COEF_FLT1_A2_L6BIT_MASK (0x3F) 

#define AUD_FLT1_EXT_COEF_FLT1_B0_L6BIT_POS (12) 
#define AUD_FLT1_EXT_COEF_FLT1_B0_L6BIT_MASK (0x3F) 

#define AUD_FLT1_EXT_COEF_FLT1_B1_L6BIT_POS (18) 
#define AUD_FLT1_EXT_COEF_FLT1_B1_L6BIT_MASK (0x3F) 

#define AUD_FLT1_EXT_COEF_FLT1_B2_L6BIT_POS (24) 
#define AUD_FLT1_EXT_COEF_FLT1_B2_L6BIT_MASK (0x3F) 

#define AUD_FLT1_EXT_COEF_RESERVED_POS (30) 
#define AUD_FLT1_EXT_COEF_RESERVED_MASK (0x3) 

/* REG_0x2E */
#define AUD_FLT2_EXT_COEF_ADDR  (AUD_LL_REG_BASE  + 0x2E*4)
#define AUD_FLT2_EXT_COEF_FLT2_A1_L6BIT_POS (0) 
#define AUD_FLT2_EXT_COEF_FLT2_A1_L6BIT_MASK (0x3F) 

#define AUD_FLT2_EXT_COEF_FLT2_A2_L6BIT_POS (6) 
#define AUD_FLT2_EXT_COEF_FLT2_A2_L6BIT_MASK (0x3F) 

#define AUD_FLT2_EXT_COEF_FLT2_B0_L6BIT_POS (12) 
#define AUD_FLT2_EXT_COEF_FLT2_B0_L6BIT_MASK (0x3F) 

#define AUD_FLT2_EXT_COEF_FLT2_B1_L6BIT_POS (18) 
#define AUD_FLT2_EXT_COEF_FLT2_B1_L6BIT_MASK (0x3F) 

#define AUD_FLT2_EXT_COEF_FLT2_B2_L6BIT_POS (24) 
#define AUD_FLT2_EXT_COEF_FLT2_B2_L6BIT_MASK (0x3F) 

#define AUD_FLT2_EXT_COEF_RESERVED_POS (30) 
#define AUD_FLT2_EXT_COEF_RESERVED_MASK (0x3) 

/* REG_0x2F */
#define AUD_FLT3_EXT_COEF_ADDR  (AUD_LL_REG_BASE  + 0x2F*4)
#define AUD_FLT3_EXT_COEF_FLT3_A1_L6BIT_POS (0) 
#define AUD_FLT3_EXT_COEF_FLT3_A1_L6BIT_MASK (0x3F) 

#define AUD_FLT3_EXT_COEF_FLT3_A2_L6BIT_POS (6) 
#define AUD_FLT3_EXT_COEF_FLT3_A2_L6BIT_MASK (0x3F) 

#define AUD_FLT3_EXT_COEF_FLT3_B0_L6BIT_POS (12) 
#define AUD_FLT3_EXT_COEF_FLT3_B0_L6BIT_MASK (0x3F) 

#define AUD_FLT3_EXT_COEF_FLT3_B1_L6BIT_POS (18) 
#define AUD_FLT3_EXT_COEF_FLT3_B1_L6BIT_MASK (0x3F) 

#define AUD_FLT3_EXT_COEF_FLT3_B2_L6BIT_POS (24) 
#define AUD_FLT3_EXT_COEF_FLT3_B2_L6BIT_MASK (0x3F) 

#define AUD_FLT3_EXT_COEF_RESERVED_POS (30) 
#define AUD_FLT3_EXT_COEF_RESERVED_MASK (0x3) 

#ifdef __cplusplus 
}                  
#endif             
